Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis

Speaker: Jack Melchert, PhD Student, Stanford University
Date: May 6, 2021

The architecture of a CGRA processing element (PE) has a significant effect on the performance and energy efficiency of an application running on the CGRA. We have developed an automated approach for generating specialized PE architectures for an application or an application domain. Frequent subgraphs mined from a set of applications are merged to form a PE architecture specialized to that application domain. Candidate PEs are then automatically pipelined, and a compiler to map applications to a CGRA using the custom PE is created. In this presentation, we will present our automated design space exploration framework and results demonstrating the power, performance, and area benefits of CGRAs with specialized PEs.