EMBER: A 100 MHz, 0.86 mm^2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry

Speaker: Akash Levy and Luke Upton, PhD Students, Stanford University  
Date: October 4, 2023

Compact and energy-efficient resistive RAM (RRAM) macros are challenging to design due to large read/write circuits that decrease storage density, low-conductance cells that increase read latency, and routing parasitics that increase read energy costs. Multiple-bits-per-cell RRAM can boost bit density, but to our knowledge, no prior demonstrations fully integrate the read/write circuitry needed for multiple-bits-per-cell storage. 

This work presents a multiple-bits-per-cell RRAM macro, which (1) demonstrates read/write circuit compaction through constrained optimization of driver and pass gate transistor sizes, (2) introduces a common-mode bleed conductance at the sense amplifier inputs, reducing read settling time by 11.35× for low conductance cells, and (3) cuts read path capacitance to further reduce read access time and energy. It is the first embedded RRAM storage macro to achieve fully-integrated multiple-bits-per-cell readout and write-verification without any off-chip reference generation or sensing. The 0.86 mm2 macro operates at 100 MHz with 64k×48 = 3M cells in 40 nm CMOS, achieving 1 b/cell read operation with 1.0 pJ/bit energy, and 2 b/cell read with 1.1 pJ/bit. Normalizing for process scaling, the macro demonstrates the highest effective RRAM cell density to date of 5.6e-3 b/F2 for 1 b/cell and 1.3e-2 b/F2 for 2 b/cell, an im- provement of 31% and 204%, respectively, over best prior work.