Enable Resource-aware Scheduling for Reconfigurable Hardware Accelerators

Speaker: Qiaoyi Liu, PhD Student, Stanford University
Date: April 12, 2023

As the demand for hardware acceleration continues to grow, optimizing the performance of reconfigurable hardware accelerators through compiler techniques is becoming increasingly critical. The AHA application mapping flow employs the clockwork compiler and unified buffer abstraction to automatically compile Halide-based applications into a graph of CGRA hardware modules. However, the current scheduler is limited in that it assumes all compute operations will have dedicated processing elements, resulting in inefficient compute resource utilization and imbalanced processing element memory ratios.

In this talk, we will discuss how to model resource constraints using modulo resource tables and develop scheduling algorithms that can optimize performance through the combination of loop pipeline and loop fusion techniques. Furthermore, we will provide valuable insights into how CGRA hardware can be adapted to support resource sharing.