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Faculty and Intel Partner

Coordinated by our partner Jeff Parkhurst at Intel, Stanford faculty involved in the AHA! effort include Mark Horowitz, Pat Hanrahan and Clark Barrett.  Scroll down for bios and info.

Jeff Parkhurst

Jeff Parkhurst is the Center Director for the ISTC for Agile HW Design. He is responsible for assisting the PIs in managing the operational details in each center as well as driving direction setting of the research. The Center Director is the primary liaison between Intel and the universities on all research and operational matters including contracts, IP, funding, and technology/knowledge transfer. Prior to this assignment, Jeff was Program Director for the Intel Science and Technology Centers for Big Data, Cloud Computing and Visual Computing. Jeff received his BS from University of Nevada at Reno in 1983 and his MS from the University of California at Davis in 1988 and his PhD at Purdue University in 1994. He is the author of numerous papers and one patent. He has been at Intel Corporation since 1994.

Mark Horowitz

Mark Horowitz received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Since 1984 he has been a professor at Stanford working in the area of digital integrated circuit design. While at Stanford he has led a number of processor designs including: MIPS-X, one of the first processors to include an on-chip instruction cache; Torch, a statically-scheduled, superscalar processor; Flash, a flexible DSM machine; and Smash, a reconfigurable polymorphic manycore processor. He has also worked in a number of other chip design areas including high-speed memory design, high-bandwidth interfaces, and fast floating point. In 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology.

Pat Hanrahan

Professor Hanrahan's current research involves rendering algorithms, high performance graphics architectures, and systems support for graphical interaction. He also has worked on raster graphics systems, computer animation and modeling and scientific visualization, in particular, volume rendering.

Clark Barrett

Clark Barrett joined Stanford University as an Associate Professor (Research) of Computer Science in September 2016. Before that, he was an Associate Professor of Computer Science at the Courant Institute of Mathematical Sciences at New York University. His expertise is in constraint solving and its applications to system verification and security. His PhD dissertation introduced a novel approach to constraint solving now known as Satisfiability Modulo Theories (SMT). Today, he is recognized as one of the world's experts in the development and application of SMT techniques. He was also an early pioneer in the development of formal hardware verification: at Intel, he collaborated on a novel theorem prover used to verify key microprocessor properties; and at 0-in Design Automation (now part of Mentor Graphics), he helped build one of the first industrially successful assertion-based verification tool-sets for hardware. He is an ACM Distinguished Scientist.

Priyanka Raina

Priyanka Raina will be starting as an Assistant Professor in Electrical Engineering at Stanford University in ​September 2018. She is currently a Visiting Research Scientist in the Architecture Research Group at NVIDIA ​Corporation. She received her Ph.D. degree in 2018 and S.M. degree in 2013 in Electrical Engineering and ​Computer Science from MIT and her B.Tech. degree in Electrical Engineering from Indian Institute of Technology ​(IIT) Delhi in 2011. ​Priyanka’s current research interests are in the area of designing energy-efficient and high-performance circuits and systems for enabling complex computational photography, computer vision and machine learning based applications on mobile and wearable devices. Her research results include the demonstration of the first hardware-accelerated systems for blind image deblurring (​awarded the best student paper award at ESSCIRC 2016 and  ​the​ 2016 ISSCC  ​s​tudent  ​r​esearch  ​p​review  ​a​ward), high-dynamic-range and low-light imaging (presented at ISSCC 2013, JSSC 2013) and real-time motion magnification in videos.


Kayvon Fatahalian

I architect high-performance visual computing systems that enable immersive and intelligent visual computing applications. In pursuit of these goals, my recent research efforts can be categorized into two main themes
  • The Visual Data Analysis Engine, a distributed computing platform -- combining ideas from high-performance image processing languages, data analytics, and database functionality -- that facilitates the development of applications that query, analyze and mine image and video collections at scale; and
  • The Graphics Engine Compiler, new programming abstractions and compiler frameworks for graphics engines of the future.