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Faculty and Intel Partners

Bio

Jeff Parkhurst

  • Center Director, ISTC for Agile HW Design

Jeff Parkhurst is the Center Director for the ISTC for Agile HW Design. He is responsible for assisting the PIs in managing the operational details in each center as well as driving direction setting of the research. The Center Director is the primary liaison between Intel and the universities on all research and operational matters including contracts, IP, funding, and technology/knowledge transfer. Beyond this, Jeff is also Center Director for the Foundational Micro Architecture Research Center which is a jointly funded venture with NSF and Program Director for the Edge Computing Center at UC Berkeley. Prior to this assignment, Jeff was Program Director for the Intel Science and Technology Centers for Big Data at MIT and Cloud Computing and Embedded Computing at CMU. Jeff received his BS from University of Nevada at Reno in 1983 and his MS from the University of California at Davis in 1988 and his PhD at Purdue University in 1994. He is the author of numerous papers and one patent. He has been at Intel Corporation since 1994.

Mark Horowitz

  • Professor, Electrical Engineering
  • Professor, Computer Science
horowitz@ee.stanford.edu

Professor Horowitz's initially focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. During this time, he built a number of early RISC microprocessors, and contributed to the design of early distributed shared memory multiprocessors. In 1990, Dr. Horowitz took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology. After returning in 1991, he research group pioneered many innovations in high-speed link design, and many of today’s high speed link designs are designed by his former students or colleagues from Rambus.

In the 2000s he started a long collaboration with Prof Levoy on computation photography, that included work that led to the Lytro camera. Dr. Horowitz's current research interests are quite broad and span using EE and CS analysis methods to problems in neuro and molecular biology to creating new agile design methodologies for analog and digital VLSI circuits. He remains interested in learning new things, and building interdisciplinary teams.

Pat Hanrahan

  • Professor, Computer Science
  • Professor, Electrical Engineering
hanrahan@cs.stanford.edu

Professor Hanrahan's current research involves rendering algorithms, high performance graphics architectures, and systems support for graphical interaction. He also has worked on raster graphics systems, computer animation and modeling and scientific visualization, in particular, volume rendering.

Clark Barrett

  • Associate Professor (Research), Computer Science
barrettc@stanford.edu

Clark Barrett joined Stanford University as an Associate Professor (Research) of Computer Science in September 2016. Before that, he was an Associate Professor of Computer Science at the Courant Institute of Mathematical Sciences at New York University. His expertise is in constraint solving and its applications to system verification and security. His PhD dissertation introduced a novel approach to constraint solving now known as Satisfiability Modulo Theories (SMT). Today, he is recognized as one of the world's experts in the development and application of SMT techniques. He was also an early pioneer in the development of formal hardware verification: at Intel, he collaborated on a novel theorem prover used to verify key microprocessor properties; and at 0-in Design Automation (now part of Mentor Graphics), he helped build one of the first industrially successful assertion-based verification tool-sets for hardware. He is an ACM Distinguished Scientist.

Kayvon Fatahalian

  • Assistant Professor, Computer Science

Kayvon Fatahalian is an assistant professor of Computer Science at Stanford University. His students work on visual computing systems projects, including large-scale video analytics, programming systems for video data mining, compilation techniques for optimizing image processing pipelines, and systems for real-time 3D graphics.

Priyanka Raina

  • Assistant Professor, Electrical Engineering
praina@stanford.edu

Priyanka Raina is an Assistant Professor in Electrical Engineering at Stanford University. Previously, she was a Visiting Research Scientist in the Architecture Research Group at NVIDIA​ ​Corporation. She received her Ph.D. degree in 2018 and S.M. degree in 2013 in Electrical Engineering and​ ​Computer Science from MIT and her B.Tech. degree in Electrical Engineering from Indian Institute of Technology​ ​(IIT) Delhi in 2011.​ Priyanka’s current research interests are designing energy-efficient and high-performance circuits and systems for image, vision and machine learning applications on mobile devices, integrating emerging non volatile memory technologies in accelerator architectures, and creating frameworks for improving hardware/software system design productivity.

Richard Bahr

  • Adjunct Professor, Electrical Engineering
bahr@stanford.edu

Academic experience:

Presently advising the Stanford SystemX Alliance, and the EE/CS AHA! Research center as an adjunct prof. Formerly the executive director of the SystemX Alliance, and a consulting professor at Stanford.

Commercial experience:

Presently an advisor, consultant and mentor to a number of startup companies primarily in the computing and wireless spaces. Formerly the SrVP responsible for Wi-Fi technology at Qualcomm, and before that the engineering executive responsible for the MIPS microprocessor and Cray supercomputer development at SGI.

Education: BSEE and MSEE from MIT.

For more extensive background, please consult my linked in profile: https://www.linkedin.com/in/rickbahr.