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Creating Better Hardware Generation Tools

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Publications | Results For: Creating Better Hardware Generation Tools
Huff, Dillon, Steve Dai, and Pat Hanrahan. “Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs”, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM51124.2021.00030.
Melchert, Jackson, Kathleen Feng, Caleb Donovick, Ross Daly, Clark Barrett, Mark Horowitz, Pat Hanrahan, and Priyanka Raina. “Automated Design Space Exploration of CGRA Processing Element Architectures Using Frequent Subgraph Analysis”, arXiv. https://doi.org/arXiv:2104.14155v1.
Kim, Sung-Jin, Zachary Myers, Steven Herbst, Byong Chan Lim, and Mark Horowitz. “20-GS/S 8b Analog-to-Digital Converter and 5-GHz Phase Interpolator for Open-Source Synthesizable High-Speed Link Applications”, IEEE Solid-State Circuits Letters, 3 (November 2020): 518-21. https://doi.org/10.1109/LSSC.2020.3037823.
Bahr, Rick, Clark Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Raj Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, and Keyi Zhang. “Creating an Agile Hardware Design Flow”, 2020 57th ACM/IEEE Design Automation Conference (DAC). http://dx.doi.org/10.1109/DAC18072.2020.9218553.
Kim, Sung-Jin, Zachary Myers, Steven Herbst, ByongChan Lim, and Mark Horowitz. “Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/S 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator”, 2020 IEEE Symposium on VLSI Circuits. https://doi.org/10.1109/VLSICircuits18222.2020.9162800.
Durst, David, Matthew Feldman, Dillon Huff, David Akeley, Ross Daly, Gilbert Bernstein, Marco Patrignani, Kayvon Fatahalian, and Pat Hanrahan. “Type-Directed Scheduling of Streaming Accelerators”, Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation (PLDI ’20). https://doi.org/10.1145/3385412.3385983.
Nayak, Ankita, Keyi Zhang, Raj Setaluri, Alex Carsello, Makai Mann, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, and Priyanka Raina. “A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). https://doi.org/10.23919/DATE48585.2020.9116477.
Yang, Xuan, Mingyu Gao, Qiaoyi Liu, Jeff Setter, Jing Pu, Ankita Nayak, Steven Bell, Kaidi Cao, Heonjae Ha, Priyanka Raina, Christos Kozyrakis, and Mark Horowitz. “Interstellar: Using Halide’s Scheduling Language to Analyze DNN Accelerators”, ASPLOS ’20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, 369–383. https://doi.org/10.1145/3373376.3378514.
Herbst, Steven, Byongchan Lim, and Mark Horowitz. “Fast FPGA Emulation of Analog Dynamics in Digitally-Driven Systems”, ICCAD ’18: Proceedings of the International Conference on Computer-Aided Design, 131 (November 2018). https://doi.org/10.1145/3240765.3240808.
Bell, Steven, Jing Pu, James Hegarty, and Mark Horowitz. “Compiling Algorithms for Heterogeneous Systems”, Synthesis Lectures on Computer Architecture, 13(1), 1-105. https://doi.org/10.2200/S00816ED1V01Y201711CAC043.