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AHA research covers multiple areas including topics related to applications, hardware generation, and validation.


We aim to create hardware for state-of-the-art applications that combine image processing and machine learning. We are looking at ways to change the programming model to address the challenges involved in lowering to hardware. We use Halide, a data-parallel DSL, to create algorithms and schedule them for different hardware backends. We modify the Halide compiler to provide analysis necessary to extract parameters for hardware mapping. Additionally, we are exploring auto-scheduling under resource constraints in Halide and a new IR, Aetherling.

  • New image and vision applications
  • Halide-to-Hardware Compiler
  • Aetherling System

CGRA Architecture and Tools

A Coarse Grain Reconfigurable Architecture (CGRA) is a reconfigurable architecture that operates on coarser granularity than traditional reconfigurable architectures such as FPGA. It contains an array of tiles, where each tile is either a processing element (PE) or a memory (MEM) tile. Our PE tiles perform arithmetic on 1-bit and 16-bit signals, while MEM tiles store and push data. The tiles communicate through configurable interconnect.

We have developed three different domain-specific languages (DSL) to generate individual components for the CGRA: PEak for PE tiles, Lake for MEM tiles, and Canal for the interconnect. Each language serves as a single source of truth for its domain, and can produce both RTL and collateral information for other tools.

  • PEak
  • Lake
  • Canal

System-on-Chip (SoC)

Two major goals underlie our SoC theme. First, we want to create an infrastructure that will facilitate the design of SoCs in general. Second, we want to design a complete system around our coarse-grained reconfigurable array (CGRA). This second goal targets a system composed of high-performance application processors, real-time cores, our CGRA, and a mix of peripherals that, together, can run full image processing applications.

Creating Better Hardware Generation Tools

Enabling agile hardware design requires solving two problems: how to provide a light-weight environment where designers can experiment at a high level to explore the solution space; and how to build a tool chain that can rapidly generate an implementation of a design choice. The key to solving both issues is creating clean design abstractions, which makes it possible to embed knowledge about optimization into the tools, enabling one to leverage other people’s tools and expertise. We plan to do this by investigating new programming language, compiler and system techniques that will aid in the development of effective hardware generation tools.

  • CoreIR
  • Magma
  • Gemstone

Improved Validation

A dramatic decrease in validation time and cost is essential for hardware construction to achieve new levels of productivity.  Validation results are required for designers to evaluate their choices and drive decisions for the next iteration of the design space exploration cycle.  Our research strives to simplify the functional verification of designs, so that designers can spend more time reasoning about the performance characteristics.  In an ideal world, designs are correct by construction, and would let the designer focus puely on performance evaluation. In practice, designers are integrating components from various sources that cannot be formally proven to be correct.  Therefore, our research efforts are focused on the rapid verification of modular systems that integrate components from many sources.  There are two major thrusts of this research: (1) the development of better formal tools for proving properties of complex modular systems, and (2) the development of better user interfaces, in the form of a domain specific programming language, for the construction of hardware verification components.  These are described in more detail in the following section:

  • CoSA
  • Fault