Skip to main content Skip to secondary navigation

System-on-Chip (SoC)

Main content start


Two major goals underlie our SoC theme. First, we want to create an infrastructure that will facilitate the design of SoCs in general. Second, we want to design a complete system around our coarse-grained reconfigurable array (CGRA). This second goal targets a system composed of high-performance application processors, real-time cores, our CGRA, and a mix of peripherals that, together, can run full image processing applications.

SoC design is quite a challenging task. The challenge emanates from the interplay of different design choices that must come together in order to produce a well-behaved system. These choices spread across power and energy requirements, performance targets, IP integration, coherence requirements, interconnect constraints, hardware/software partitioning, and the different protocols used for on-chip and off-chip communications. Most designers, however, tackle this challenge in a layered-fashion: power/energy envelops and performance targets are defined and then the architectural decisions on the rest of the system are derived. In this regard, our goal is to capture this layered approach into a framework that facilitates the inference and validation of design parameters across layers, which will ultimately lead to automated design flow.

Garnet SOC