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Resources Overview

Our open-source and related resources include Stanford's Halide-to-Hardware compiler, along with Ofer Shacham's Genesis2 and multiple other hardware generation tools created specifically for taping out our chip(s) (see below).

In the past we have also used James Hegarty's Darkroom compiler for image processing applications along with John Brunhaver's hardware-generating back-end.

AHA Open-Source Software

Halide-to-hardware is a tool for taking unmodified Halide algorithms, plus user-specified schedule information, and producing the means for accelerating the algorithm with automatically-generated special-purpose hardware, system calls and drivers. Other open-source tools we created to build our latest chip Garnet include

  •     Garnet - AHA second-generation CGRA
  •     Lassen - PE used in Garnet
  •     Gemstone - Chip generator infrastructure based on Magma
  •     Peak - Specification language for processing elements (CPUs)
  •     Canal - Specification language for intertile routing
  •     Magma - A hardware design language embedded in python
  •     Fault - A Python package for testing hardware (part of the magma ecosystem)

Also see the extensive list of reasources found here: https://github.com/StanfordAHA/doc

Related Resources

Genesis2 (Stanford) (github) is a chip generator originally developed at Stanford University, available free of charge for non-commercial academic and research purposes under Stanford's Academic Use Agreement.  For commercial use contact Stanford's OTL Office of Technology Licensing.

Halide is a new programming language designed to make it easier to write high-performance image processing code on modern machines. Its current front end is embedded in C++. Compiler targets include x86/SSE, ARM v7/NEON, CUDA, Native Client, and OpenCL.  Halide source is available on github.

RISC-V is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed at the University of California, Berkeley.