Thoughts on High-speed Links

Speaker: Prof. Mark Horowitz, Stanford University
Date: February 8, 2023

Over the past couple decades, the achievable bandwidths of high-speed links have increased dramatically, with some modern electrical links running at 100⁺Gb/s per differential channel, allowing a 1TB off a chip. This talk will introduce some old rules of thumb which I learned during my work on links over a decade ago. If these limits still hold, without a major technology change, the symbol rates of links are likely to saturate soon, which means the push will be to either increase bits/symbol, or the number of parallel links. How to do the former has been well explored in lower symbol rate systems, but because of backward dependencies is hard to apply to high symbol rate systems. I show a new (to us) approach to break these dependencies. In the parallel approach I will extrapolate from what I learned from Rambus to discuss what I think is really holding back using many parallel optical channels to scale chip bandwidths.