Presentation
Main content start
AHA Monthly Meeting Presentations
Towards Efficient Verification of Quantized Neural Networks
Pei Huang, Stanford University (April 3, 2024)Memory Consistency Model-Aware Cache Coherence for Heterogeneous Shared Memory Systems
Rachel Cleaveland, PhD Student, Stanford University (February 7, 2024)Clover: Closed-Loop Verifiable Code Generation
Ying Sheng, PhD Student, Stanford University (December 6, 2023)PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM
Anjiang Wei, PhD Student, Stanford University (October 4, 2023)EMBER: A 100 MHz, 0.86 mm^2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry
Akash Levy and Luke Upton, PhD Students, Stanford University (October 4, 2023)Life Post Moore’s Law: The New CAD Frontier
Prof. Mark Horowitz, Stanford University (July 19, 2023)Deegen: A Meta-compiler Approach for High Performance VMs at Low Engineering Cost
Haoran Xu, PhD Student, Stanford University (July 19, 2023)Biology Needs Computer Architects: Keeping Up with Genomic-scale Data
Sneha Goenka, PhD Student, Stanford University (June 14, 2023)G-QED Pre-silicon Verification
Saranyu Chattopadhyay, PhD Student, Stanford University (June 14, 2023)Mosaic: An Interoperable Compiler for Tensor Algebra
Manya Bansal, Undergraduate Student, Stanford University (May 10, 2023)Generalizing Rewrite Rule Synthesis
Ross Daly, PhD Student, Stanford University (April 12, 2023)Enable Resource-aware Scheduling for Reconfigurable Hardware Accelerators
Qiaoyi Liu, PhD Student, Stanford University (April 12, 2023)A Scalable Formal Approach for Correctness-Assured Hardware Design
Dr. Jin Yang, Intel Labs (March 8, 2023)Agile Application-Centric Design of Reconfigurable Analog Circuits
Yu-Neng Wang, PhD Student, Stanford University (March 8, 2023)Thoughts on High-speed Links
Prof. Mark Horowitz, Stanford University (February 8, 2023)Verified Agile Hardware
Jackson Melchert, PhD Student, Stanford University (February 8, 2023)Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Jackson Melchert, PhD Student, Stanford University (January 11, 2023)DALA: Distribution-Agnostic Level Allocation for Multiple Bits-Per-Cell RRAM
Anjiang Wei, PhD Student, Stanford University (December 14, 2022)SpDISTAL: Compiling Distributed Sparse Tensor Computations
Rohan Yadav, PhD Student, Stanford University (December 14, 2022)Summary of the PCAST Report on Revitalizing the U.S. Semiconductor Ecosystem
Prof. Priyanka Raina, Stanford University (October 5, 2022)Hardware and Software for Sparse ML
Prof. Fredrik Kjolstad, Stanford University (October 5, 2022)Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
Ankita Nayak, PhD Student, Stanford University (July 13, 2022)Developing FPGAs as an Acceleration Platform for Data-Intensive Applications
James Thomas, PhD Student, Stanford University (July 13, 2022)Bringing Source-Level Debugging Frameworks to Hardware Generators
Keyi Zhang, PhD Student, Stanford University (May 4, 2022)A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion
Kavya Sreedhar, PhD Student, Stanford University (May 4, 2022)Verified Optimization and Mapping of Sparse Tensor Algebra
Scott Kovach, PhD Student, Stanford University (April 6, 2022)The Use of MLIR in Magma
Raj Setaluri, PhD Student, Stanford University (April 6, 2022)Programming Systems for Reconfigurable Analog Hardware
Sara Achour, Assistant Professor, Stanford University (March 2, 2022)Automatic pipelining for CGRA Applications - Techniques, Analysis and Future Directions
Jackson Melchert, PhD Student, Stanford University (February 9, 2022)Building DSLs in Python
Caleb Donovick, PhD Student, Stanford University (December 9, 2021)